Field-effect transistors (FETs), that exemplify solid-state electronic transistors, are three-terminal devices that operate based on the field effect. Referring to FIG. 1A, when operating a FET 10, a voltage applied to a terminal 12 called the “Gate Electrode” acts on mobile charge carriers remotely through a front barrier 14 which may be insulating, weakly conducting, or semiconducting. The mobile charge carriers get pulled into/depleted from a “channel” region 16, by means of electrostatic fields.
The gate electrode 12 may form or disrupt a conductive “bridge” in the channel region 16 between two other terminals 18, 20 called the “Source Electrode” and the “Drain Electrode”, respectively, depending on: (a) the voltage magnitude and voltage polarity applied externally to the gate electrode 12; (b) the polarity of charge being pulled into, or depleted from, the channel 16 by the gate 12 (negative for electrons, positive for electron vacancies also known as “holes”); and (c) the polarity and quantity of immobile fixed charges either present in the channel 16 or in the front barrier 14. Other structures of the FET 10 may include a conducting cap 22 disposed on the front barrier 14, which in turn is disposed on the channel 16. The channel 16 may be disposed on a back barrier 24, which in turn is disposed on a substrate 26. A pulse doping layer 28 may be disposed within the front barrier 14, with the pulse doping layer 28 being, for example, an n++ or donor of electrons traveling from the source 18 to the drain 20.
For clarity of exposition, as described herein, an arrangement where a “HIGH” voltage applied to the gate terminal 12 attracts negatively charged electrons into an otherwise weakly conducting channel 16, thereby forming a conducting path that electrically bridges the electron-rich source 18 and drain 20. On the other hand, application of a “LOW” gate voltage would then disrupt the conducting path, thus electrically isolating the source 18 and drain 20. This is called an n-channel FET, meaning that the carriers of electric current are negatively charged electrons.
FETs are classified as depletion-mode (“D-Mode”) or enhancement-mode (“E-Mode”) transistors based on the maximum value of the “LOW” voltage beyond which appreciable conduction occurs. If the device starts conducting at a “LOW” voltage which is negative, it is called a D-Mode FET. If it takes a positive “LOW” voltage for the device to start conducting, so that there is no appreciable current when the gate is at 0 Volt, it is called an E-Mode FET.
A high-electron mobility transistor (HEMT) in the prior art is illustrated in FIG. 1A, which is a FET in which the front barrier 14 is a semiconductor as well, usually an alloy different in elemental composition from the material of the channel 14. With a semiconducting front barrier 14, it is easier in practice to insert fixed electrical charges that would further modulate the response of electrons in the channel 16 to the gate voltage. A variant of the basic HEMT structure in the prior art, shown as the FET 30 in FIG. 2, features two delta-doped layers 32, 34, one in each barrier 36, 38, respectively, such as described in Lin et al., “A Delta-Doped InGaP/InGaAs PHEMT with Different Doping Profiles for Device-Linearity Improvement”, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 54, No. 7, July 2007, pp. 1617-1625.
The operation of the FET is best visualized by means of a partial “band energy diagram”, which is the energy of the edge of the conduction band (CB) pictured as a function of spatial position. The band energy diagrams, such as shown in FIG. 1D, are constructed such that, under the prevalent electrostatic fields, electrons tend to pool near the bottom of the profile. The dashed lines show the “chemical potential” (also known as Fermi level) which may be considered an energy reference for the CB. It is important to note that the lower the CB energy relative to this reference at any point, the larger the electron concentration at that point.
FIG. 1D shows the band energy diagram in a vertical section through the center of FIG. 1A, cutting through the gate metal, front barrier, channel, back barrier and substrate. The barriers are made of a semiconductor of a different material or alloy composition than the channel. An example plot of material elemental composition vs. vertical location is illustrated in FIG. 1E. As shown in FIG. 1D, with such a material stack, a conduction band “well” forms at the barrier-channel interface, where electrons can be made to pool by increasing the gate voltage, as explained below. This pool of electrons, once created by applying a large enough gate voltage, would bridge the source and drain terminals and allow an electrical current.
FIGS. 1B-1C show schematically the CB energy as a function of position in the channel, across the device of FIG. 1A from source to drain terminals. If the gate voltage is very low, the CB energy in the channel under the gate electrode is high, presenting a potential step that blocks electrons from transferring from source to drain, even if the drain CB energy is lower than that of the source. As the gate voltage increases, the step height decreases, until a threshold gate voltage is reached. At this threshold voltage (also known as “pinch-off voltage”), electrons in the source can gain enough energy from random thermal excitations to overcome the step, as shown in FIG. 1C, after which they are accelerated by the drain voltage into the drain terminal, providing current at the drain terminal.
FIGS. 3A-3B display exemplary plots of the drain current ID versus the gate-to-source voltage VGs. The source is chosen to be the zero of potential throughout the present disclosure. A fixed positive voltage is applied to the drain to collect the electrons launched from the source. This drain voltage is often close to the highest DC voltage in the system, such as the positive power supply rail. As described herein, a threshold voltage is present during which the drain current is small, followed by an abrupt increase as the potential step becomes low enough to be surmounted by electrons thermally excited from the source. Beyond this point, the current at the drain monotonically increases as the increasing gate voltage attracts more and more electrons into the channel. FIG. 3A represents a D-Mode FET, since the threshold voltage for conduction to begin is negative, while FIG. 3B represents an E-Mode FET, since the threshold voltage is positive.
In the prior art, the influence of FET electrical characteristics by another terminal, different from the source, drain, and gate, has long been investigated as a nuisance effect. The other terminal, as a “fourth terminal”, considered in the prior art typically belongs to a different device on the same chip, causing nominally isolated devices on the same chip to become electrically coupled. This coupling is through (a) direct current injection by the fourth terminal, (b) indirect modulation of the channel potential through charging or discharging interface traps beneath the channel, or (c) direct electrostatic modulation of the channel potential. Such unwanted coupling to a fourth terminal has been labelled “back-gating” or “side-gating” in the prior art, such as in Boroumand et al., “Observations of Backgate Impedance Dispersion in GaAs Isolation Structures”, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 48, No. 9, September 2011, pp. 1850-1858; Kocot et al., “Backgating in GaAs MESFET's”, IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, Vol. MTT-30, No. 7, July 1982, pp. 963-968; and Chen et al., “Reduction of Sidegating in GaAs Analog and Digital Circuits Using a New Buffer Layer”, IEEE TRANSACTIONS ON ELECTRON DEVICES, Vol. 36, No. 9, September 1989, pp. 1546-1556. Effect (c) has been neglected in such studies since typical inter-device separations are on the order of tens of microns. Occasionally, a substrate contact is termed the “back-gate”, as described in the prior art in Norman Fadhil Idham et al., “Device Characteristics of HEMT Structures Based on Backgate Contact Method”, ICSE2006 Proc. 2006, pp. 740-742; but its large distance from the channel, on the order of hundreds of microns, and its isolation due to the highly resistive substrate makes the substrate contact unusable for purposes of threshold voltage control.
An underlying n-doped (donor-doped) layer has been utilized as an investigative tool to examine charge-potential characteristics of free GaAs surfaces, as described in the prior art such as Kawaharazuka et al., “Study of Free GaAs Surfaces Using a Back-gated Undoped GaAs/AlGaAs Heterostructure, PHYSICA E, Vol. 13, 2002, pp. 663-666. The Kawaharazuka reference (a) describes essentially a 3-terminal device viewed upside-down, and (b) serves a different purpose to that in the present inventive disclosure. Additionally, it is to be noted that n-doped layers, if attempted to be used as threshold-control terminal (TCT) access layers, are incompatible with dual E/D-Mode operation with a single power supply. This is because E-mode operation in such a hypothetical device would need a negative voltage applied to the n-doped layer.
A highly resistive p-doped layer underneath the channel has been reported in a MESFET device, such as described in Bayruns et al., “The Bootstrapped Gate FET (BGFET)—A New Control Transistor”, GaAs IC Symposium, 1995, pp. 136-139. Its purpose was to improve the linearity of the FET current-voltage characteristics under high-frequency operation. The high resistivity required of the p-doped layer for realizing such a linear FET would make for a poorly controlled threshold voltage in the the present inventive disclosure.
Earlier attempts at single power-supply FET operation have utilized quasi-enhancement mode FETs. These have a slightly positive threshold voltage, so that the current drawn when nominally off; i.e. the gate voltage is 0 volts, is smaller than when nominally on, but not negligible. Special additional circuitry is required to prevent off-state power dissipation, as described in the prior art in Abey et al., “A Single Supply High Performance PA MMIC for GSM Handsets using Quasi-Enhancement Mode PHEMT”, IEEE MTT-S Digest, 2001, pp. 923-926.